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HSP48410/883
TM
Data Sheet
May 1999
FN3542.2
Histogrammer/Accumulating Buffer
The Intersil HSP48410/883 is an 84 lead Histogrammer IC int.ended for use in image and signal analysis. The on board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size of 4k x 4k with no possibility of overflow. In addition to 4-Histogramming, the HSP48410 can generate and store the Cumulative Distribution Function for use in Histogram Equalization Applications. Other capabilities of the HSP48410 include: Bin Accumulation, Look Up Table, 24-bit Delay Memory, and Delay and Subtract Mode. A flash clear pin is available in all modes of operation and performs a single cycle reset on all locations of the internal memory array and all internal data paths. The HSP48410 includes a fully asynchronous interface which provides a means for communications with a host, such as a microprocessor. The interface includes dedicated Read/Write pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 10-Bit Pixel Data * 4k x 4k Frame Sizes * Asynchronous Flash Clear Pin * Fully Asynchronous 16-Bit or 24-Bit Host Interface * DC to 33MHz Clock Rate
Applications
* Histogramming * Histogram Equalization * Image and Signal Analysis
Ordering Information
PART NUMBER HSP48410GM-33/883 HSP48410GM-25/883 TEMP. RANGE ( oC) PACKAGE -55 to 125 -55 to 125 84 Ld PGA 84 Ld PGA PKG. NO. G84.A G84.A
Block Diagram
HISTOGRAM MEMORY ARRAY MUX DATA IN DATA OUT ADDER DIO0-23 DIO INTERACE
DIN0-23
PIN0-9 ADDRESS GENERATOR IOADD0-9
ADDRESS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HSP48410/883 Pinouts
84 PIN PGA TOP VIEW
11 10
DIN8 DIN5
DIN10 DIN7
DIN11 DIN9
DIN13 DIN12
DIN16 DIN15
DIN17 DIN21
DIN19 DIN20
DIN22 DIN23
DIO23 DIO21
DIO22 DIO20
DIO19 DIO17
9
DIN4
DIN6
DIN14
GND
DIN18
DIO18
DIO16 DIO14
8
DIN2
DIN3
DIO15
7
PIN9
DIN0
GND
DIO10
DIO12
DIO11
6 5
VCC PIN8
DIN1 PIN7
CLK PIN6
DIO9 DIO6
DIO8
DIO13
DIO7
GND
4 3 2
PIN5 PIN3
PIN4 PIN1 FCT0 IOADD9 IOADD8
DINO4 DIO1
DINO5 DIO3
PIN2
FC
RD
FCT2
WR
UWS
IOADD6 IOADD3 IOADD0
DIO0
DIO2
PIN "A1" ID
1
PIN0 A
START B
LD C
FCT1 D
GND E
IOADD5 IOADD7 IOADD4 IOADD2 IOADD1 F G H J K
VCC L
84 PIN PGA BOTTOM VIEW
DIN19 DIO17
DIO22 DIO20
DIO23 DIO21
DIN22 DIN23
DIN19 DIN20
DIN17 DIN21
DIN16 DIN15
DIN13 DIN12
DIN11 DIN9
DIN10 DIN7
DIN8 DIN5
11 10
DIO16
DIO18
DIN18
GND
DIN14
DIN6
DIN4 DIN2
9
DIO14
DIO15
DIN3
8
DIO11
DIO12
DIO10
GND
DIN0
DIN9
7
DIO13
DIO8 DIO7
DIO9 DIO6
CLK PIN6
DIN1
VCC PIN8
6 5
GND
PIN7
DIO5 DIO3
DIO4 DIO4 IOADD8 IOADD9 FCT0
PIN4 PIN1
PIN5 PIN3
4 3
DIO2
DIO0
IOADD3 IOADD3 IOADD6
UWS
WR
FCT2
RD
FC
PIN2
2
VCC L
IOADD1 IOADD2 IOADD4 IOADD7 IOADD5 K J H G F
GND E
FCT1 D
LD C
START B
PIN0 A
1
2
HSP48410/883 Pin Description
SYMBOL CLK C6 PIN NUMBER TYPE I DESCRIPTION Clock Input. This input has no effect on the chips functionality when the chip is programmed to an asynchronous mode. All signals denoted as synchronous have their timing specified with reference to this signal. Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on chip RAM with address values in Histogram, Bin Accumulate and LUT (write) mode. During Asynchronous modes it is unused. The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below). These three pins are decoded to determine the mode of operation for the chip. The signals are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the loading of this function is asynchronous to CLK, it is necessary to disable the START pin during loading and enable START at least 1 CLK cycle following the LD pulse. This pin informs the on chip circuitry which clock cycle will start and/or stop the current mode of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously started and stopped. This input is sampled by the rising edge of CLK. The actual function of this input depends on the mode that is selected. START must always be held high (disabled) when changing modes. This will provide a smooth transition from one mode to the next by allowing the part to reconfigure itself before new mode begins. When START is high, LUT (read) mode is enabled except for Delay and Subtract Modes. Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits in the RAM Array and the input and output data paths to zero. Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and Delay and Subtract Modes. Synchronous to CLK.
PIN0-9
A1-5, A7, B3-5, C5
I
LD
C1
I
FCT0-2
D1-2, E3
I
START
B1
I
FC
B2
I
DIN0-23
A8-11, B6-11, C10-11, D10-11, E9-11, F10-11, G9-11, H10-11 J5-7, J10-11, K2-11, L2-4, L6-11
I
DIO0-23
I/O
Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the memory array and reading the results of the previous operation. Configurable as either a 24-bit or 16-bit bus. RAM Address in Asynchronous Modes. Sampled on the falling edge of WR or RD.
IOADD0-9
F1, F3, G1-3, H1-2, J1-2, K1 F2
I
UWS
I
Upper Word Select. In 16-bit asynchronous mode, a one on this pin denotes the contents of DIO0-7 as being the upper eight-bits of the data in or out of the Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect. Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one of the asynchronous modes. Asynchronous to CLK. Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23 in other modes. Asynchronous to CLK. +5V. Ground.
WR
E2
I
RD
C2
I
VCC GND
A6, L1 C7, E1, F9, L5
3
HSP48410/883
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8V Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to VCC +0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 36 7.0 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.46 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,500
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER Logical One Input Voltage Logical Zero Input Voltage High Level Clock Input Low Level Clock Input Output High Voltage SYMBOL VIH VIL V IHC VILC VOH VOL IL IO ICCSB CONDITIONS VCC = 5.5V VCC = 4.5V VCC = 5.5V VCC = 4.5V IOH = -400A, VCC = 4.5V (Note 2) IOL = +2.0mA, VCC = 4.5V (Note 2) VIN = VCC or GND, VCC = 5.5V VOUT = VCC or GND, VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 25.6MHz, VIN = VCC or GND VCC = 5.5V (Note 3) (Notes 4, 5) GROUP A SUBGROUP 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 3.0 2.6 MAX 0.8 0.8 UNITS V V V V V
Output Low Voltage
1, 2, 3
-
0.4
V A A A
Input Leakage Current
1, 2, 3
-10
10
I/O Leakage Current
1, 2, 3
-10
10
Standby Supply Current
1, 2, 3
-
500
Operating Power Supply Current
ICCOP
1, 2, 3
-55 TA 125
-
308
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
-
2. Interchanging of force and sense conditions is permitted. 3. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 12mA/MHz. Maximum junction temperature must be considered when operating part at high clock frequencies. 4. Tested as follows: f = 1MHz, VIH = 2.6V, VIL = 0.4V, VOH 1.5V, VOL 1.5V, VIHC = 3.4V and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF.
4
HSP48410/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: V CC = 5.0V 10%, TA = -55oC to 125oC (Note 1) -33 (33MHz) PARAMETER Clock Period Clock Low Clock High DIN Setup DIN 0-23 Hold Clock to DIO 0-23 Valid FC Pulse Width FCT 0-2 Setup to LD FCT 0-2 Hold from LD START Setup to CLK START Hold from CLK PIN 0-9 Setup Time PIN 0-9 Hold Time LD Pulse Width LD Setup to START WR Low WR High Address Setup Address Hold DIO Setup to WR DIO Hold from WR RD Low RD High RD Low to DIO Valid Output Enable Time Read/Write Cycle Time NOTES: 6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK) = 2.0V, (all others) = 1.5V. Output load circuit with CL= 40pF. Output transition measured at V OH 1.5V and VOL 1.5V. 7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. 8. Transition is measured at 200 mV from steady state voltage with loading as specified in test load circuit with CL= 40pF. SYMBOL t CP t CH t CL t DS t DH t DO t FL t FS t FH t SS t SH t PS t PH t LL t LS t WL t WH t AS t AH t WS t WH t RL t RH t RD t OE t CY Note 8 Note 7 NOTES GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMP ( oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 30 12 12 15 1 35 12 1 15 0 15 1 12 tCP 15 15 16 2 16 2 43 17 65 43 19 MAX 19 -25 (25.6MHz) MIN 39 15 15 16 1 35 15 1 16 0 16 1 15 tCP 20 20 20 2 20 2 55 20 80 MAX 24 55 24 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
HSP48410/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS -33 (33MHz) PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VCC = Open, f = 1MHz, all measurements are referenced to device GND. VCC = Open, f = 1MHz, all measurements are referenced to device GND. NOTES 9 TEMP (oC) TA = 25 MIN MAX 12 -25 (25.6MHz) MIN MAX 12 UNITS pF
Output Capacitance
CO
9
TA = 25
-
12
-
12
pF
DIO Valid After RD High Output Disable Time Output Rise Time Output Fall Time NOTES:
t OH t OD tr tf From 0.8V to 2.0V From 2.0V to 0.8V
9, 10
-55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
0
-
0
-
ns
9, 10 9, 10 9, 10
-
27 9 9
-
27 9 9
ns ns ns
9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
6
HSP48410/883 Waveforms
t CP t CH CLK t CL
t DS DIN0-23
t DH
t PS PIN0-9
t PH
t DO DIO0-23
t SS t SH START t SH t SS
FC
t FL
FIGURE 1. SYNCHRONOUS DATA AND CONTROL TIMING
tLL
LD
tFS tFH FCT0-2
CLK
tLS START
FIGURE 2. FUNCTION LOAD TIMING
7
HSP48410/883 Waveforms
RD
(Continued)
t OE DIO0-23
t OD
FIGURE 3. SYNCHRONOUS OUTPUT TIMING
t WL WR
t WH
RD t AH t AS IOADD0-9 t WDS DIO0-23 t WDH
FIGURE 4. WRITE CYCLE TIMING
WR t RL RD t AS IOADD0-9 t OD t OH t AH t RH
t RD DIO0-23
FIGURE 5. READ CYCLE TIMING
tr 2.0V 0.8V
tf
FIGURE 6. OUTPUT RISE AND FALL TIMES
8
HSP48410/883 Burn-In Circuits
84 PIN PGA TOP VIEW
11 10
DIN8 DIN5
DIN10 DIN7
DIN11 DIN9
DIN13 DIN12
DIN16 DIN15
DIN17 DIN21
DIN19 DIN20
DIN22 DIN23
DIO23 DIO21
DIO22 DIO20
DIO19 DIO17
9
DIN4
DIN6
DIN14
GND
DIN18
DIO18
DIO16 DIO14
8
DIN2
DIN3
DIO15
7
PIN9
DIN0
GND
DIO10 DIO9
DIO12
DIO11
6 5
VCC PIN8
DIN1 PIN7
CLK PIN6
DIO8
DIO13
DIO6
DIO7
GND
4 3
PIN5 PIN3
PIN4 PIN1 FCT0 IOADD9 IOADD8
DINO4 DIO1
DINO5 DIO3
2
PIN2
FC
RD
FCT2
WR
UWS
IOADD6 IOADD3 IOADD0
DIO0
DIO2
PIN "A1" ID
1
PIN0 A
START B
LD C
FCT1 D
GND E
IOADD5 IOADD7 IOADD4 IOADD2 IOADD1 F G H J K
VCC L
9
HSP48410/883
TABLE 5. PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 PIN NAME PIN0 PIN2 PIN3 PIN5 PIN8 VCC PIN9 DIN2 DIN4 DIN5 DIN8 START FC PIN1 PIN4 PIN7 DIN1 DIN0 DIN3 BURN-IN SIGNAL F1 F3 F4 F6 F9 VCC F10 F3 F5 F6 F9 F10 F16 F2 F5 F8 F2 F1 F4 PGA PIN B9 B10 B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 PIN NAME DIN6 DIN7 DIN10 LD RD PIN6 CLK GND DIN9 DIN11 FCT1 FCT2 DIN12 DIN13 GND WR FCT0 DIN14 DIN15 BURN-IN SIGNAL F7 F8 F11 F11 F1 F7 F0 GND F10 F12 F13 F14 F13 F14 GND F2 F12 F15 F1 PGA PIN E11 F1 F2 F3 F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 PIN NAME DIN16 IOADD5 UWS IOADD9 GND DIN21 DIN17 IOADD7 IOADD6 IOADD8 DIN18 DIN20 DIN19 IOADD4 IOADD3 DIN23 DIN22 IOADD2 IOADD0 BURN-IN SIGNAL F2 F6 F11 F10 GND F7 F3 F8 F7 F9 F4 F6 F5 F5 F4 F9 F8 F3 F1 PGA PIN J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 NOTES: 11. V CC/2 (2.7V 10%) used for outputs only. 12. 47k (20%) resistor connected to all pins except VCC and GND. 13. V CC = 5.5 0.5V. 14. 0.1F (min) capacitor between VCC and GND per position. 15. FO = 100kHz 10%, F1 = F0/2, F2 = F1/2 . . . F16 = F15/2, 40% - 60% duty cycle. 16. Input Voltage Limits: VIL = 0.8V max. VIH = 4.5V 10%. PIN NAME DIO6 DIO9 DIO10 DIO21 DIO23 IOADD1 DIO0 DIO1 DIO4 DIO7 DIO8 DIO12 DIO15 DIO18 DIO20 DIO22 VCC DIO2 DIO3 DIO4 BURN-IN SIGNAL F7 F10 F11 F7 F9 F2 F1 F2 F5 F8 F9 F13 F1 F4 F6 F8 VCC F3 F4 F6
Die Characteristics
DIE DIMENSIONS: 330 x 281 x 19 1mils METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 0.47 x 105 A/cm 2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10

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